NETWORK DELAY SIMULATOR PLUS

PORT A to PORT B Path >>

Data Source A
No Delays
	ms delay (5-4095)
	bit delay (16-65535)
BERT 511 generator
Loopback from PortB Working Data Clock Range

Delay Control with Data

Burst Errors
	Duration (1-4095ms)
	Interval (1-16383ms)
Type Error
Error Rate 1x10^-n

Random Errors
	Type
	Error Rate 1x10^-n
Create Single Bit Error

PORT B to PORT A Path <<

Data Source B
No Delays
	ms delay (5-4095)
	bit delay (16-65535)
BERT 511 generator
Loopback from PortA Working Data Clock Range

Delay Control with Data

Burst Errors
	Duration (1-4095ms)
	Interval (1-16383ms)
Type Error
Error Rate 1x10^-n

Random Errors
	Type
	Error Rate 1x10^-n
Create Single Bit Error

Data Clock Sources (Note: Check-boxes in front of the clock selections below are used to invert the clock.)

z	Port A to Port B Buffer>>	z
	Port A to Port B Buffer>>

z	Port B to Port A <<Buffer	z
	Port B to Port A <<Buffer

Enable External Reference Clock with divisor of (1-256)

The following RTS/CTS delays are only applicable when both ports are DCE.
Port A RTS/CTS delay
Port B RTS/CTS delay

East Coast Datacom, Inc.
245 Gus Hipp Boulevard
Suite 3
Rockledge FL. USA 32955-4812

Business Hours 7:00AM to 5:00PM EST
Support: (321) 637-9922
www.ecdata.com

On the physical box this button is used
to display the assigned IP Address via
the front panel LEDs.

This is used to submit a BERT Tester change.

The text in this button will change to REDwhen
any of the BERT Tester options have been changed.
This is a reminder that the desired changes have
not yet been sent to the RDS+ unit.

This is used to cancel a BERT Tester change and
return the selected items to the previous setting.

The cancel is complete when the Submit button
is no longer RED.

One of these three radio buttons enables or
disables the BERT Tester.

One of these two radio buttons selects
the mode of the BERT Tester.

This is used to submit Data Delay and/or Error Generation changes
on the Port A to Port B path.

The text in this button will change to RED when any of the Path
options have been changed.
This is a reminder that the desired changes have not yet been
sent to the RDS+ unit.

This is used to cancel any Path Delay and/or Error Generation changes
and return the selected items to their previous setting.

The cancel is complete when the Submit button is no longer RED.

This is the RXC
data clock as read
at Port A.

This is the TXC
data clock as read
at Port A.

One of these four radio buttons enables
or disables Data Delays on the
PortA to PortB Path.

Enabling the BERT Generator disables
the Data Delay buffer on this path.

Checking this box enables loopback
at Port B so that data received into
Port A is looped back out Port A.

To ensure the accuracy of an expected Data Delay in Milliseconds,
the correct Port A data clock range must be selected.
If this range is incorrect the Data Delay will operate but the
desired MS delay will be inaccurate.

Check this box to delay the RTS control signal along with the above set Data Delay.

Check the box to enable Burst Errors
on the PortA to PortB Path.

Burst errors will occur for a burst of
milliseconds as set by Duration, then
the an Interval of selected milliseconds
will pass until the next burst.
The type and rate of error during the
burst period can be selected.

Check the box to enable Random
Errors on the PortA to PortB Path.

Random errors will occur
continuously at the Rate selected.

Clicking this link generates a
single one-time bit error on
the PortA to PortB Path.

All settings and buttons on the PortB to PortA Path are the same as in PortA to PortB Path above.

This is used to submit a Data Clock Source change.

The text in this button will change to RED when any of the Clock Source options have been changed.
This is a reminder that the desired changes have not yet been sent to the RDS+ unit.

This is used to cancel any Data Clock Source changes and return
the selected items to their previous setting.

The cancel is complete when the Submit button is no longer RED.

This is used to specify what interface board
is physically in Port A.

The data clock sources are automatically set
to default values for the boards that are
selected here.

This is used to specify what interface board
is physically in Port B.

The data clock sources are automatically set
to default values for the boards that are
selected here.

The client browser must initiate periodic updates from the RDS+ unit. The frequency of this update is set here.

Here the Internal Clock Generator frequency can be selected. This clock is available as a Data Clock source. It is not used for any other internal functions.

Check this box to enable the External Reference Clock. The External Reference Clock is not a direct data clock source. It is available to synchronize the RDS+ internal clocking with an external reference. A valid external clock reference must be 8KHz. The divisor can be set to divide the external reference clock down to the required 8KHz. The maximum allowable external clock is 2.048MHz which when divided by 256 yeilds the required 8KHz.

This is the Data Clock Source selection area. The number of selectable fields is dependent on what interface board types are configured in PortA and PortB. The checkbox in front of each clock selection is to allow for inversion. If the box is checked then the clock source will be inverted.