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Tail Circuit Buffers

Allows DCE to DCE Connections with built in data Buffers

The RDS-TCB Tail-Circuit Buffer is designed to provide selectable bi-directional buffering between two data circuits that are operating at nominally the same clock rate and are capable of providing clocking as a DCE. In such cases, the timing of the two circuits is not locked to the same timing source, or may be allowed to deviate from a com-mon timing source for a length of time. The RDS-TCB meets this need by pro-viding selectable amounts of bi-directional memory from 1,024 bits up to 8,192 bits and supports synchronous clock rates up to 2.048 Mbps.

press to get the RDS-TCB: HTML Spec Sheet PDF Spec Sheet